Study of wafer warpage reduction by dicing street

• Published in: Japanese Journal of Applied Physics Vol. 61; no. SJ; p. SJ1001
• Main Authors: Feng, Wei, Shimamoto, Haruo, Kawagoe, Tsuyoshi, Honma, Ichirou, Yamasaki, Masato, Okutsu, Fumitake, Masuda, Takatoshi, Kikuchi, Katsuya
• Format: Journal Article
• Language: English
• Published: Tokyo IOP Publishing 01-08-2022; Japanese Journal of Applied Physics
• Subjects: Design optimization; FEM simulation; Finite element method; measurement; Reduction; representative volume element (RVE) method; wafer warpage; Warpage
• ISSN: 0021-4922; 1347-4065
• DOI: 10.35848/1347-4065/ac61ab

Wafer warpage occurs during the fabrication process, which induces many issues such as wafer handling, lithography alignment, device reliability. The efficiency of dicing street on wafer warpage reduction is investigated by varying the width, depth, and pitch of dicing. With the finite element method simulation results, decreasing the dicing pitch to a quarter-pitch shows a 43.7% warpage reduction. We reveal that the method of decreasing the dicing pitch is more efficient on wafer warpage reduction than that of increasing the dicing width or depth. Furthermore, the efficiency of warpage reduction by decreasing the dicing pitch is confirmed by experiments, which shows a good agreement with the simulated results. The method of decreasing the dicing pitch cut each part smaller. These small parts deform locally instead of continually over the whole wafer, resulting in an efficient wafer warpage reduction. This research provides guidelines for chiplet design or optimization of chip size to reduce the wafer warpage.