A Layout-Based Rad-Hard DICE Flip-Flop Design

• Published in: Journal of electronic testing Vol. 35; no. 1; pp. 111 - 117
• Main Authors: Wang, Haibin, Dai, Xixi, Ibrahim, Younis Mohammed Younis, Sun, Hongwen, Nofal, Issam, Cai, Li, Guo, Gang, Shen, Zicai, Chen, Li
• Format: Journal Article
• Language: English
• Published: New York Springer US 01-02-2019; Springer Nature B.V
• Subjects: CAE) and Design; Circuits and Systems; Computer simulation; Computer-Aided Engineering (CAD; Electrical Engineering; Engineering; Latches; Layouts; Semiconductor devices; Single event upsets; Strikes; Transistors; Charge sharing; LEAP DICE; Single event upset; DICE; Rad-hard flip-flop
• ISSN: 0923-8174; 1573-0727
• DOI: 10.1007/s10836-019-05773-4

The DICE flip-flop has been rendered ineffective in deep-submicron technology nodes (e.g. 65 nm and 28 nm) due to charge sharing when exposed to single event strikes. This paper presents a new single event upset tolerant flip-flop design by applying the hardening technique on DICE at the layout level. This approach is an alternative to existing Layout Design through Error-Aware Transistor Positioning (LEAP); it also re-places transistors in master and slave DICE latches in the zigzag fashion in the layout. Both computer simulations and heavy-ion experimental results demonstrate that our proposed layout design has no single event upset errors under normal strikes until LET = 37 MeV·cm
2
/mg compared to the traditional DICE structure.