A study of the trench surface inversion problem in the trench CMOS technology

• Published in: IEEE electron device letters Vol. 4; no. 9; pp. 303 - 305
• Main Authors: Cham, K.M., Chiang, S.-Y.
• Format: Journal Article
• Language: English
• Published: New York, NY IEEE 01-09-1983; Institute of Electrical and Electronics Engineers
• Subjects: Applied sciences; CMOS process; CMOS technology; Doping profiles; Electronics; Exact sciences and technology; Implants; Impurities; Isolation technology; Microelectronic fabrication (materials and surfaces technology); MOSFETs; Paper technology; Performance gain; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Voltage; Simulation; Complementary MOS technology; Microelectronic fabrication
• ISSN: 0741-3106; 1558-0563
• DOI: 10.1109/EDL.1983.25742

This paper presents the results obtained in the study of the trench surface inversion problem for the CMOS technology using trench isolation. Special emphasis is put on the n-well CMOS technology where the inversion problem is most severe. Potential distribution along the trench surface is simulated using the SUPREM and GEMINI programs for different bias conditions, as well as for different impurity doping profiles and fixed charge densities (Q ss ). The results showed that Q ss along the trench surface has to be maintained at 5 × 10 10 cm -2 if the substrate doping concentration remains at 6 × 10 14 cm -3 . Higher substrate doping, lower n-well bias, and more negative substrate bias will help prevent trench surface inversion. p-well CMOS is more suitable for trench isolation due to the higher doping concentration inside the p-well. Experimental data showed that trench isolation gives no improvement in latch-up susceptibility when the trench surface is inverted.