A novel self-aligned highly reliable sidewall split-gate flash memory

• Published in: IEEE transactions on electron devices Vol. 53; no. 3; pp. 465 - 473
• Main Authors: Caleb Yu-Sheng Cho, Ming-Jer Chen, Chiou-Feng Chen, Tuntasood, P., Fan, D.-T., Tseng-Yi Liu
• Format: Journal Article
• Language: English
• Published: New York, NY IEEE 01-03-2006; Institute of Electrical and Electronics Engineers; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Acceptability; Applied sciences; Architecture; Blocking; Corners; Design. Technologies. Operation analysis. Testing; Devices; Electronics; Endurance; Exact sciences and technology; Flash memory; Flash memory (computers); Integrated circuits; Integrated circuits by function (including memories and processors); Magnetic and optical mass memories; MOSFETs; NAND; NOR; overerase; poly erase; Programming; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; sidewall; source-side injection; split-gate; Storage and reproduction of information; Transistors; Cell structure; Memory devices; MOSFET; sidewall; split-gate; Retention factor; Erasure; overerase; poly erase; NAND; Floating gate technology; MOSFETs; Self aligned technology; NOR; Electric field; Manufacturing defect; Flash memory; Manufacturing process; 16 bit Processor; Integrated circuit; Recording; source-side injection
• ISSN: 0018-9383; 1557-9646
• DOI: 10.1109/TED.2005.863764

A self-aligned sidewall split-gate Flash memory cell is fabricated with overerase immunity. Particularly, the sidewall corner of the floating-gate is deliberately rounded to release the electric field lines encountered in the poly-to-poly erase. The unit cell size of 12.7 F/sup 2/ (F is the feature size), formed in a 32-Mb NOR architecture, and the acceptable erase speed of 20 ms for block erase (512 K bits, 16 pages) are quite competitive. Endurance cycles up to 10/sup 5/ confirm the novel cell to be highly reliable as compared with the conventional source-side erase scheme. The bake experiment at 250/spl deg/C before and after program/erase cycles indicates the cell not only free of extrinsic defects in the manufacturing process but also experiencing excellent retention characteristics. Disturb effects during the programming and read-out operations are examined in detail and the operating conditions for disturbs inhibition are readily determined. We eventually elaborate on the differences between the proposed cell structure and existing ones, as well as on the NAND architecture application.