Coplanar Full Adder in Quantum-Dot Cellular Automata via Clock-Zone-Based Crossover

• Published in: IEEE transactions on nanotechnology Vol. 14; no. 3; pp. 497 - 504
• Main Authors: Abedi, Dariush, Jaberipur, Ghassem, Sangsefidi, Milad
• Format: Journal Article
• Language: English
• Published: IEEE 01-05-2015
• Subjects: Adders; carry flow adder; Clocks; Computer architecture; Full adder; Logic gates; Microprocessors; Quantum-dot cellular Automata; Robustness; Wires; carry flow adder; Quantum-dot cellular automata; full adder
• ISSN: 1536-125X; 1941-0085
• DOI: 10.1109/TNANO.2015.2409117

We use a coplanar QCA crossover architecture in the design of QCA full adders that leads to reduction of QCA cell count and area consumption without any latency penalty. This crossover uses non-adjacent clock zones for the two crossing wires. We further investigate the impact of these gains on carry flow QCA adders. These designs have been realized with QCADesigner, evaluated, and tested for correctness. For better performance comparison with previous relevant works, we use a QCA-specific cost function, as well as the conventional evaluation method. We show 23% cell count and 48% area improvements over the best previous QCA full adder design. Similar results for 4-, 8-, 16-, 32-, and 64-bit adders are 29% (22%), 24% (51%), 19% (54%), 13% (69%), and 9% (49%) cell count reduction (less area consumption), respectively.