N-channel FinFETs With 25-nm Gate Length and Schottky-Barrier Source and Drain Featuring Ytterbium Silicide

• Published in: IEEE electron device letters Vol. 28; no. 2; pp. 164 - 167
• Main Authors: Lee, R.T.P., Lim, A.E.-J., Kian-Ming Tan, Tsung-Yang Liow, Guo-Qiang Lo, Samudra, G.S., Dong Zhi Chi, Yee-Chia Yeo
• Format: Journal Article
• Language: English
• Published: New York, NY IEEE 01-02-2007; Institute of Electrical and Electronics Engineers; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Applied sciences; Barriers; CMOS; Design. Technologies. Operation analysis. Testing; Devices; Dielectrics; Drains; Electronics; Electrons; Etching; Exact sciences and technology; Fabrication; FinFET; FinFETs; Gates; Integrated circuits; Intermetallics; MOSFETs; multiple-gate transistor; rare earth metal; Schottky; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Silicidation; silicide; Silicides; Silicon compounds; Transistors; YbSi; Ytterbium; MOSFET; Multiple gate transistor; FinFET; n channel; Dual gate transistor; silicide; Self aligned technology; Schottky; Siliconizing; Manufacturing process; Complementary MOS technology; Spacer; YbSi; rare earth metal; Barrier height; multiple-gate transistor; Schottky barrier
• ISSN: 0741-3106; 1558-0563
• DOI: 10.1109/LED.2006.889233

We have fabricated n-channel 25-nm gate length FinFETs with Schottky-barrier source and drain featuring a self-aligned ytterbium silicide (YbSi 1.8 ). A low-temperature silicidation process was developed for the formation of the low electron barrier height YbSi 1.8 phase, without reaction with SiO 2 isolation or SiN spacer materials, enabling integration in a CMOS fabrication process flow. The fabricated device exhibits good device characteristics with a drive current of 241 muA/mum at V DS =V GS -V t =1 V, I on /I off =10 4 at V DS =1.1 V, subthreshold swing of 125 mV/decade, and drain-induced barrier lowering of 0.26 V/V