Novel dual bit tri-gate charge trapping memory devices

• Published in: IEEE electron device letters Vol. 25; no. 12; pp. 810 - 812
• Main Authors: Specht, M., Kommling, R., Hofmann, F., Klandzievski, V., Dreeskornfeld, L., Weber, W., Kretz, J., Landgraf, E., Schulz, T., Hartwich, J., Rosner, W., Stadele, M., Luyken, R.J., Reisinger, H., Graham, A., Hartmann, E., Risch, L.
• Format: Journal Article
• Language: English
• Published: New York, NY IEEE 01-12-2004; Institute of Electrical and Electronics Engineers; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Applied sciences; Channels; Charge injection; charge-trapping memory; Cycles; Data storage; Design. Technologies. Operation analysis. Testing; Devices; Dielectric devices; Dielectrics; Dry etching; Electronics; Electrostatics; Exact sciences and technology; Fabrication; Gates; Integrated circuits; Integrated circuits by function (including memories and processors); Lithography; Magnetic and optical mass memories; Memory devices; Microelectronic fabrication (materials and surfaces technology); Nonvolatile memory; Rapid thermal processing; Scalability; semiconductor device fabrication; Semiconductor devices; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Silicon; Storage and reproduction of information; Trapping; tri-gate transistor; Memory devices; charge-trapping memory; Retention factor; Transistor gate; tri-gate transistor; Charge carrier trapping; Microelectronic fabrication; Non volatile memory; Charge injection; Integrated circuit; semiconductor device fabrication; Miniaturization; Planar technology
• ISSN: 0741-3106; 1558-0563
• DOI: 10.1109/LED.2004.838621

Dual bit operation of fabricated tri-gate nonvolatile memory devices with aggressively scaled oxide-nitride-oxide (ONO) dielectrics is presented for the first time. Compared to a planar cell, the proposed tri-gate device architecture offers higher readout currents and improved electrostatic gate control of the channel region yielding very good scalability of the devices. We have investigated devices with gate lengths in the range L/sub G/=100-220 nm and we focus on their write-erase, retention, and cycling characteristics.