GPU Acceleration of the Most Apparent Distortion Image Quality Assessment Algorithm

• Published in: Journal of imaging Vol. 4; no. 10; p. 111
• Main Authors: Holloway, Joshua, Kannan, Vignesh, Zhang, Yi, Chandler, Damon, Sohoni, Sohum
• Format: Journal Article
• Language: English
• Published: Basel MDPI AG 01-10-2018
• Subjects: Accuracy; Algorithms; Computer memory; Computing time; Constraint modelling; Distortion; GPU computing; Graphics processing units; Hierarchies; Image quality; image quality assessment; International conferences; Kernels; Most Apparent Distortion; Multimedia; Neural networks; performance analysis; Quality; Quality assessment; Visual perception driven algorithms; Wavelet transforms; United States > US; Arizona; Germany
• ISSN: 2313-433X; 2313-433X
• DOI: 10.3390/jimaging4100111

The primary function of multimedia systems is to seamlessly transform and display content to users while maintaining the perception of acceptable quality. For images and videos, perceptual quality assessment algorithms play an important role in determining what is acceptable quality and what is unacceptable from a human visual perspective. As modern image quality assessment (IQA) algorithms gain widespread adoption, it is important to achieve a balance between their computational efficiency and their quality prediction accuracy. One way to improve computational performance to meet real-time constraints is to use simplistic models of visual perception, but such an approach has a serious drawback in terms of poor-quality predictions and limited robustness to changing distortions and viewing conditions. In this paper, we investigate the advantages and potential bottlenecks of implementing a best-in-class IQA algorithm, Most Apparent Distortion, on graphics processing units (GPUs). Our results suggest that an understanding of the GPU and CPU architectures, combined with detailed knowledge of the IQA algorithm, can lead to non-trivial speedups without compromising prediction accuracy. A single-GPU and a multi-GPU implementation showed a 24× and a 33× speedup, respectively, over the baseline CPU implementation. A bottleneck analysis revealed the kernels with the highest runtimes, and a microarchitectural analysis illustrated the underlying reasons for the high runtimes of these kernels. Programs written with optimizations such as blocking that map well to CPU memory hierarchies do not map well to the GPU’s memory hierarchy. While compute unified device architecture (CUDA) is convenient to use and is powerful in facilitating general purpose GPU (GPGPU) programming, knowledge of how a program interacts with the underlying hardware is essential for understanding performance bottlenecks and resolving them.