Modeling and Application of Multi-Port TSV Networks in 3-D IC

• Published in: IEEE transactions on computer-aided design of integrated circuits and systems Vol. 32; no. 4; pp. 487 - 496
• Main Authors: Wei Yao, Siming Pan, Achkir, B., Jun Fan, Lei He
• Format: Journal Article
• Language: English
• Published: IEEE 01-04-2013
• Subjects: 3-D integration; Capacitance; conductance and capacitance (RLGC) matrices; crosstalk; Impedance; Inductance; Integrated circuit modeling; modeling; packaging; power delivery; resistance; Silicon; Solid modeling; through-silicon via (TSV); Through-silicon vias
• ISSN: 0278-0070; 1937-4151
• DOI: 10.1109/TCAD.2012.2228740

Through-silicon-via (TSV) enables vertical connectivity between stacked chips or interposer and is a key technology for 3-D integrated circuits (ICs). While arrays of TSVs are needed in 3-D IC, there only exists a frequency-dependent resistance, inductance, conductance and capacitance circuit model for a pair of TSVs with coupling between them. In this paper, we develop a simple yet accurate circuit model for a multiport TSV network (e.g., coupled TSV array) by decomposing the network into a number of TSV pairs and then applying circuit models for each of them. We call the new model a pair-based model for the multiport TSV network. It is first verified against a commercial electromagnetic solver for up to 20 GHz and subsequently employed for a variety of examples for signal and power integrity analysis.