Influence of N-Well Contact Area on the Pulse Width of Single-Event Transients

• Published in: IEEE transactions on nuclear science Vol. 58; no. 6; pp. 2585 - 2590
• Main Authors: Ahlbin, J. R., Atkinson, N. M., Gadlage, M. J., Gaspard, N. J., Bhuva, B. L., Loveless, T. D., Zhang, E. X., Chen, L., Massengill, L. W.
• Format: Journal Article
• Language: English
• Published: New York IEEE 01-12-2011; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: CMOS integrated circuits; Contact; Digital circuits; Digital design; Inverters; Logic gates; Mathematical analysis; MOSFETs; Parasitic BJT; Pulse measurements; Pulse width; single event; Single event transient; Single event upset; Transient analysis
• ISSN: 0018-9499; 1558-1578
• DOI: 10.1109/TNS.2011.2172221

Heavy-ion broadbeam results from a 90 nm process are presented for five inverter chains with varying n-well contact schemes. Results show that inverters with the smallest percentage of n-well contact area within an n-well produced the longest and most frequent single-event transients (SETs). As the percentage of n-well area contacted increases above 2%, the pulse width and number of SETs levels-off. A result indicating an optimized percentage of n-well area contacted can be calculated that minimizes the pulse width and number of SETs in a digital circuit.