A vertical submicron polysilicon thin-film transistor using a low temperature process

A vertical submicron polysilicon thin-film transistor using a low temperature process

This letter presents a submicron (0.5 μ) vertical N-channel MOS thin-film transistor (TFT) fabricated in Polycrystalline Si using a simple low temperature process (/spl les/600/spl deg/C). The channel length is determined by the thickness of an SiO 2 film. As a result, submicron vertical polysilicon...

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Bibliographic Details
Published in:IEEE electron device letters Vol. 15; no. 10; pp. 415 - 417
Main Authors: Tiemin Zhao, Min Cao, Saraswat, K.C., Plummer, J.D.
Format: Journal Article
Language:English
Published: IEEE 01-10-1994
Subjects:
Active matrix liquid crystal displays
Amorphous materials
Crystallization
Etching
Lithography
Semiconductor films
Silicon
Substrates
Temperature
Thin film transistors
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Summary:This letter presents a submicron (0.5 μ) vertical N-channel MOS thin-film transistor (TFT) fabricated in Polycrystalline Si using a simple low temperature process (/spl les/600/spl deg/C). The channel length is determined by the thickness of an SiO 2 film. As a result, submicron vertical polysilicon TFT's can be fabricated without submicron lithographic equipment that is not yet available for large area active matrix liquid crystal display (AMLCD) applications. The device has a dynamic range of greater than five orders of magnitude after hydrogenation.
Bibliography:ObjectType-Article-2
SourceType-Scholarly Journals-1
ObjectType-Feature-1
content type line 23
ISSN:0741-3106
1558-0563
DOI:10.1109/55.320986