Defining Statistical Timing Sensitivity for Logic Circuits With Large-Scale Process and Environmental Variations

• Published in: IEEE transactions on computer-aided design of integrated circuits and systems Vol. 27; no. 6; pp. 1041 - 1054
• Main Authors: Xin Li, Jiayong Le, Celik, M., Pileggi, L.T.
• Format: Journal Article
• Language: English
• Published: New York IEEE 01-06-2008; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Algorithm design and analysis; Algorithms; Circuit analysis computing; Circuits; Delay; Effectiveness; Fluctuations; Large-scale systems; Logic circuits; Nanomaterials; Nanostructure; Optimization methods; Probability; Process variations; Random variables; sensitivity; Sensitivity analysis; statistical static timing analysis; Time measurements; Timing
• ISSN: 0278-0070; 1937-4151
• DOI: 10.1109/TCAD.2008.923241

The large-scale process and environmental variations for today's nanoscale ICs require statistical approaches for timing analysis and optimization. In this paper, we demonstrate why the traditional concept of slack and critical path becomes ineffective under large-scale variations and propose a novel sensitivity framework to assess the ldquocriticalityrdquo of every path, arc, and node in a statistical timing graph. We theoretically prove that the path sensitivity is exactly equal to the probability that a path is critical and that the arc (or node) sensitivity is exactly equal to the probability that an arc (or a node) sits on the critical path. An efficient algorithm with incremental analysis capability is developed for fast sensitivity computation that has linear runtime complexity in circuit size. The efficacy of the proposed sensitivity analysis is demonstrated on both standard benchmark circuits and large industrial examples.