A RISC-V ISA Extension for Ultra-Low Power IoT Wireless Signal Processing

• Published in: IEEE transactions on computers Vol. 71; no. 4; pp. 766 - 778
• Main Authors: Amor, Hela Belhadj, Bernier, Carolynn, Prikryl, Zdenek
• Format: Journal Article
• Language: English
• Published: New York IEEE 01-04-2022; The Institute of Electrical and Electronics Engineers, Inc. (IEEE); Institute of Electrical and Electronics Engineers
• Subjects: Bluetooth; Demodulation; Energy costs; Engineering Sciences; Hardware; Internet of Things; IoT; LoRa; Power consumption; Power demand; Protocols; Quadratures; RISC-V ISA extension; Signal processing; Simulation; software-defined radio; Transceivers; ultra-low power (ULP) transceiver architecture; Wireless communication; ultra-low power (ULP) transceiver architecture; Bluetooth; software-defined radio; ISA extension; LoRa; IoT
• ISSN: 0018-9340; 1557-9956
• DOI: 10.1109/TC.2021.3063027

This article presents an instruction-set extension to the open-source RISC-V ISA (RV32IM) dedicated to ultra-low power (ULP) software-defined wireless IoT transceivers. The custom instructions are tailored to the needs of 8/16/32-bit integer complex arithmetic typically required by quadrature modulations. The proposed extension occupies only two major opcodes and most instructions are designed to come at a near-zero energy cost. Both an instruction accurate (IA) and a cycle accurate (CA) model of the new architecture are used to evaluate six IoT baseband processing test benches including FSK demodulation and LoRa preamble detection. Simulation results show cycle count improvements from 19 to 68 percent. Post synthesis simulations for a target 22nm FD-SOI technology show less than 1 percent power and 28 percent area overheads, respectively, relative to a baseline RV32IM design. Power simulations show a peak power consumption of 380 µW for Bluetooth LE demodulation and 225 µW for LoRa preamble detection (BW = 500 kHz, SF = 11).