TSV-Cluster Defect Tolerance Using Tree-Based Redundancy for Yield Improvement of 3-D ICs

• Published in: IEEE transactions on computer-aided design of integrated circuits and systems Vol. 40; no. 8; pp. 1500 - 1510
• Main Authors: Maity, Dilip Kumar, Roy, Surajit Kumar, Giri, Chandan
• Format: Journal Article
• Language: English
• Published: New York IEEE 01-08-2021; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: 3-D integrated circuit (3-D IC); Circuit faults; dedicated-spare; Delays; Failure rates; Fault tolerant systems; Integrated circuits; Interconnections; Maintenance engineering; Power consumption; Redundancy; Repair; shared-spare; Through-silicon vias; through-silicon-via (TSV); yield
• ISSN: 0278-0070; 1937-4151
• DOI: 10.1109/TCAD.2020.3021341

Through silicon via (TSV)-based 3-D integrated circuit (3-D IC) has several advantages like high density, high bandwidth, and low-power consumption. However, many defects in TSV are evolved during the fabrication and bonding process. In practice, faulty TSVs tend to be clustered. Employing spare TSVs (s-TSVs) is an acceptable method for repairing faulty TSVs. This article introduces a tree-based TSV repair framework to utilize hardware resources more efficiently for a higher repair rate. The proposed architecture partitions the s-TSVs for a different level of redundancy sharing. Experimental results show that the proposed design consumes <inline-formula> <tex-math notation="LaTeX">11.01~\mu m^{2} </tex-math></inline-formula> area per signal TSV to achieve 99.99% yield for 0.05% failure rate. The proposed architecture also exhibits a higher repair rate of 73.33% for heavily clustered faults. Moreover, for the same number of functional and s-TSVs, the proposed approach reduces the delay overhead efficiently compared to the prior works.