Quasi-planar bulk CMOS technology for improved SRAM scalability

A simple approach for manufacturing quasi-planar bulk MOSFET structures is demonstrated and shown to be effective not only for improving device performance but also for reducing variation in 6T-SRAM read and write margins, in an early 28nm CMOS technology. With optimization of the pocket implant dos...

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Published in:	Solid-state electronics Vol. 65-66; pp. 184 - 190
Main Authors:	Shin, Changhwan, Tsai, Chen Hua, Wu, Mei Hsuan, Chang, Chung Fu, Liu, You Ren, Kao, Chih Yang, Lin, Guan Shyan, Chiu, Kai Ling, Fu, Chuan-Shian, Tsai, Cheng-tzung, Liang, Chia Wen, Nikolić, Borivoje, Liu, Tsu-Jae King
Format:	Journal Article Conference Proceeding
Language:	English
Published:	Kidlington Elsevier Ltd 01-11-2011 Elsevier
Subjects:	Applied sciences Channels CMOS Design. Technologies. Operation analysis. Testing Electronics Exact sciences and technology Implants Integrated circuits Integrated circuits by function (including memories and processors) MOSFET MOSFETs Optimization Pocket Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices SRAM Transistors Variability Voltage MOSFET CMOS SRAM Variability Performance evaluation Static random access memory Scalability Random access memory Optimization Low voltage Non volatile memory Complementary MOS technology Integrated circuit Manufacturing Planar technology
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Abstract	A simple approach for manufacturing quasi-planar bulk MOSFET structures is demonstrated and shown to be effective not only for improving device performance but also for reducing variation in 6T-SRAM read and write margins, in an early 28nm CMOS technology. With optimization of the pocket implant doses, voltage scaling is facilitated. Since its benefits increase with decreasing channel width, quasi-planar bulk MOSFET technology should be advantageous for future CMOS technology generations (22nm and beyond).
AbstractList	A simple approach for manufacturing quasi-planar bulk MOSFET structures is demonstrated and shown to be effective not only for improving device performance but also for reducing variation in 6T-SRAM read and write margins, in an early 28 nm CMOS technology. With optimization of the pocket implant doses, voltage scaling is facilitated. Since its benefits increase with decreasing channel width, quasi-planar bulk MOSFET technology should be advantageous for future CMOS technology generations (22 nm and beyond). A simple approach for manufacturing quasi-planar bulk MOSFET structures is demonstrated and shown to be effective not only for improving device performance but also for reducing variation in 6T-SRAM read and write margins, in an early 28nm CMOS technology. With optimization of the pocket implant doses, voltage scaling is facilitated. Since its benefits increase with decreasing channel width, quasi-planar bulk MOSFET technology should be advantageous for future CMOS technology generations (22nm and beyond).
Author	Wu, Mei Hsuan Chang, Chung Fu Tsai, Chen Hua Tsai, Cheng-tzung Kao, Chih Yang Nikolić, Borivoje Liu, You Ren Chiu, Kai Ling Fu, Chuan-Shian Liu, Tsu-Jae King Lin, Guan Shyan Shin, Changhwan Liang, Chia Wen
Author_xml	– sequence: 1 givenname: Changhwan surname: Shin fullname: Shin, Changhwan email: shinch@eecs.berkeley.edu organization: Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, CA 94720, USA – sequence: 2 givenname: Chen Hua surname: Tsai fullname: Tsai, Chen Hua organization: United Microelectronics Corporation, Hsinchu, Taiwan, ROC – sequence: 3 givenname: Mei Hsuan surname: Wu fullname: Wu, Mei Hsuan organization: United Microelectronics Corporation, Hsinchu, Taiwan, ROC – sequence: 4 givenname: Chung Fu surname: Chang fullname: Chang, Chung Fu organization: United Microelectronics Corporation, Hsinchu, Taiwan, ROC – sequence: 5 givenname: You Ren surname: Liu fullname: Liu, You Ren organization: United Microelectronics Corporation, Hsinchu, Taiwan, ROC – sequence: 6 givenname: Chih Yang surname: Kao fullname: Kao, Chih Yang organization: United Microelectronics Corporation, Hsinchu, Taiwan, ROC – sequence: 7 givenname: Guan Shyan surname: Lin fullname: Lin, Guan Shyan organization: United Microelectronics Corporation, Hsinchu, Taiwan, ROC – sequence: 8 givenname: Kai Ling surname: Chiu fullname: Chiu, Kai Ling organization: United Microelectronics Corporation, Hsinchu, Taiwan, ROC – sequence: 9 givenname: Chuan-Shian surname: Fu fullname: Fu, Chuan-Shian organization: United Microelectronics Corporation, Hsinchu, Taiwan, ROC – sequence: 10 givenname: Cheng-tzung surname: Tsai fullname: Tsai, Cheng-tzung organization: United Microelectronics Corporation, Hsinchu, Taiwan, ROC – sequence: 11 givenname: Chia Wen surname: Liang fullname: Liang, Chia Wen organization: United Microelectronics Corporation, Hsinchu, Taiwan, ROC – sequence: 12 givenname: Borivoje surname: Nikolić fullname: Nikolić, Borivoje organization: Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, CA 94720, USA – sequence: 13 givenname: Tsu-Jae King surname: Liu fullname: Liu, Tsu-Jae King organization: Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, CA 94720, USA
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Keywords	MOSFET CMOS SRAM Variability Performance evaluation Static random access memory Scalability Random access memory Optimization Low voltage Non volatile memory Complementary MOS technology Integrated circuit Manufacturing Planar technology
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SubjectTerms	Applied sciences Channels CMOS Design. Technologies. Operation analysis. Testing Electronics Exact sciences and technology Implants Integrated circuits Integrated circuits by function (including memories and processors) MOSFET MOSFETs Optimization Pocket Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices SRAM Transistors Variability Voltage
Title	Quasi-planar bulk CMOS technology for improved SRAM scalability
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