Quasi-planar bulk CMOS technology for improved SRAM scalability

• Published in: Solid-state electronics Vol. 65-66; pp. 184 - 190
• Main Authors: Shin, Changhwan, Tsai, Chen Hua, Wu, Mei Hsuan, Chang, Chung Fu, Liu, You Ren, Kao, Chih Yang, Lin, Guan Shyan, Chiu, Kai Ling, Fu, Chuan-Shian, Tsai, Cheng-tzung, Liang, Chia Wen, Nikolić, Borivoje, Liu, Tsu-Jae King
• Format: Journal Article Conference Proceeding
• Language: English
• Published: Kidlington Elsevier Ltd 01-11-2011; Elsevier
• Subjects: Applied sciences; Channels; CMOS; Design. Technologies. Operation analysis. Testing; Electronics; Exact sciences and technology; Implants; Integrated circuits; Integrated circuits by function (including memories and processors); MOSFET; MOSFETs; Optimization; Pocket; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; SRAM; Transistors; Variability; Voltage; MOSFET; CMOS; SRAM; Variability; Performance evaluation; Static random access memory; Scalability; Random access memory; Optimization; Low voltage; Non volatile memory; Complementary MOS technology; Integrated circuit; Manufacturing; Planar technology
• ISSN: 0038-1101; 1879-2405
• DOI: 10.1016/j.sse.2011.06.022

A simple approach for manufacturing quasi-planar bulk MOSFET structures is demonstrated and shown to be effective not only for improving device performance but also for reducing variation in 6T-SRAM read and write margins, in an early 28nm CMOS technology. With optimization of the pocket implant doses, voltage scaling is facilitated. Since its benefits increase with decreasing channel width, quasi-planar bulk MOSFET technology should be advantageous for future CMOS technology generations (22nm and beyond).