Intermittent Resonant Clocking Enabling Power Reduction at Any Clock Frequency for Near/Sub-Threshold Logic Circuits

• Published in: IEEE journal of solid-state circuits Vol. 49; no. 2; pp. 536 - 544
• Main Authors: Fuketa, Hiroshi, Nomura, Masahiro, Takamiya, Makoto, Sakurai, Takayasu
• Format: Journal Article
• Language: English
• Published: New York IEEE 01-02-2014; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Adders; Arrays; Clocks; LC resonance; Logic gates; near-threshold circuit; Resistance; resonant clocking; Resonant frequency; RLC circuits; subthreshold circuit; ultra-low power
• ISSN: 0018-9200; 1558-173X
• DOI: 10.1109/JSSC.2013.2294172

In order to eliminate the limitation of a narrow frequency range of conventional resonant clocking, intermittent resonant clocking (IRC) is proposed for near/sub-threshold logic circuits. In this paper, IRC is applied to 0.37 V 32-bit adder array with latches and adder array with flip-flops fabricated in a 40 nm CMOS process. Measurement results show that IRC reduces the clock power by 36% at 980 kHz and the clock leakage power by 81% compared with conventional non-resonant clocking when IRC is applied to the adder array with latches. The same power reduction is achieved when IRC is applied to the adder array with flip-flops. IRC can reduce the clock power at any clock frequency, which enables flexible selection of the clock frequency.