Programmable ASIPs for Multimode MIMO Transceiver

• Published in: Journal of signal processing systems Vol. 90; no. 10; pp. 1369 - 1381
• Main Authors: Shahabuddin, Shahriar, Silvén, Olli, Juntti, Markku
• Format: Journal Article
• Language: English
• Published: New York Springer US 01-10-2018; Springer Nature B.V
• Subjects: Algorithms; Circuits and Systems; Computer Imaging; Electrical Engineering; Engineering; Enumeration; Error detection; Image Processing and Computer Vision; Mean square errors; MIMO communication; Pattern Recognition; Pattern Recognition and Graphics; Signal,Image and Speech Processing; System effectiveness; Transceivers; Vision; Wireless communication systems; Wireless communications; TTA; MIMO; OFDM; VLSI; ASIP
• ISSN: 1939-8018; 1939-8115
• DOI: 10.1007/s11265-018-1341-3

Application specific instruction-set processors (ASIP) are a programmable and flexible alternative of traditional finite state machine (FSM) controlled register-transfer level (RTL) designs for multimode basedband systems. In this paper, we present two ASIPs for small scale multiple-input multiple-output (MIMO) wireless communication systems that demonstrate the soundness and effectiveness of ASIPs for this type of applications. The first ASIP is programmed with multiple MIMO symbol detection algorithms for 4 × 4 systems. The supported detection algorithms are minimum mean-square error (MMSE), two variants of the selective spanning with fast enumeration (SSFE) and
K
-best list sphere detection (LSD). The second ASIP supports MMSE and zero-forcing dirty paper coding (ZF-DPC) algorithms for a base station (BS) with 4 antennas and for 4 users. Both ASIPs are based on transport triggered architecture (TTA) and are programmed with a retargetable compiler with high level language to meet the time-to-market requirements. The detection and precoding algorithms can be switched in the respective ASIPs based on the error-rate requirements. Depending on the algorithms, MIMO detection ASIP delivers 6.16–66.66 Mbps throughput at a clock frequency of 200 MHz on 90 nm technology. The precoder ASIP provides a throughput of 52.17 and 51.95 Mbps for MMSE and ZF-DPC precoding respectively at a clock frequency of 210 MHz on 90 nm technology.