A 36-V 49% Efficient Hybrid Charge Pump in Nanometer-Scale Bulk CMOS Technology

• Published in: IEEE journal of solid-state circuits Vol. 52; no. 3; pp. 781 - 798
• Main Authors: Ismail, Yousr, Haechang Lee, Pamarti, Sudhakar, Chih-Kong Ken Yang
• Format: Journal Article
• Language: English
• Published: New York IEEE 01-03-2017; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: All-nMOS charge pump (CP); Breakdown voltage; Charge pumps; CMOS; CMOS technology; device stacking; double-diode substrate isolation; Efficiency; high voltage; hybrid CP (HCP); Metal oxide semiconductors; MOS devices; polysilicon diode; Power efficiency; Substrates; Switches; Switching circuits; Transistors
• ISSN: 0018-9200; 1558-173X
• DOI: 10.1109/JSSC.2016.2636876

This paper introduces a hybrid charge pump (HCP) architecture. The HCP enables high-voltage dc outputs in a nanometer-scale CMOS technology at improved power efficiency by optimally mixing different charge pump (CP) types that trade off voltage range and power efficiency. Conventional CP outputs in a bulk CMOS process are limited to a single-diode breakdown voltage (~12 V in a 65-nm technology node). To support >12 V outputs, the HCP extends the voltage tolerance of bulk CMOS substrates via two technology methods: double-diode substrate isolation and field oxide isolation. To enable these isolation methods, two specialized CP cells are devised: an all-nMOS voltage doubler and an improved-drive Dickson-type pump. Two HCP design examples with opposite voltage polarities are implemented in a 65-nm CMOS technology, and their measurement results are discussed. The positive voltage HCP achieves a 36 V output and 49% peak efficiency at a 20-μA load current and occupies 0.18 mm 2 in area. This output voltage represents a 3× increase in the technology's voltage range compared to ranges attainable by conventional designs.