Gate protection for vertical gallium nitride trench MOSFETs: The buried field shield

• Published in: e-Prime Vol. 5; no. C; p. 100218
• Main Authors: Binder, Andrew T., Cooper, James A., Steinfeldt, Jeffrey, Allerman, Andrew A., Floyd, Richard, Yates, Luke, Kaplar, Robert J.
• Format: Journal Article
• Language: English
• Published: United Kingdom Elsevier Ltd 01-09-2023; Elsevier
• Subjects: Buried field shield; Gallium nitride; Gate oxide protection; Trench MOSFET; Vertical GaN; Vertical GaN; Trench MOSFET; Gallium nitride; Gate oxide protection; Buried field shield
• ISSN: 2772-6711; 2772-6711
• DOI: 10.1016/j.prime.2023.100218

•Lines 7-8: Furthermore, state-of-the-art vertical GaN devices including fin-JFETs, CAVETs, and MOSFETs have been reported with blocking voltages up to 1.6 kV [ 4, 5, 6].•Lines 99-101: Consequently, no leakage ramp-up or avalanche behavior was observed. On average, devices only reached 30% of the theoretical blocking voltage before failing. Several factors can reduce the robustness of the gate dielectric such as material defects, non-uniform thickness, and interface roughness. Further associated challenges will be discussed Section 4.•Lines 148-149: It should be noted that initial reports on regrown devices such as fin JFETs are emerging [ 4 ], however, the leakage currents are excessively high compared to traditional commercial offerings.
This paper describes a process for forming a buried field shield in GaN by an etch-and-regrowth process, which is intended to protect the gate dielectric from high fields in the blocking state. GaN trench MOSFETs made at Sandia serve as the baseline to show the limitations in making a trench gated device without a method to protect the gate dielectric. Device data coupled with simulations show device failure at 30% of theoretical breakdown for devices made without a field shield. Implementation of a field shield reduces the simulated electric field in the dielectric to below 4 MV/cm at breakdown, which eliminates the requirement to derate the device in order to protect the dielectric. For realistic lithography tolerances, however, a shield-to-channel distance of 0.4 μm limits the field in the gate dielectric to 5 MV/cm and requires a small margin of device derating to safeguard a long-term reliability and lifetime of the dielectric.