Multiplierless Implementations of MF/DTMF Receivers

• Published in: IEEE transactions on communications Vol. 32; no. 7; pp. 839 - 847
• Main Authors: Agarwal, R., Sudhakar, R., Agrawal, B.
• Format: Journal Article
• Language: English
• Published: New York, NY IEEE 01-01-1984; Institute of Electrical and Electronics Engineers
• Subjects: Algorithm design and analysis; Applied sciences; Digital filters; Digital signal processing chips; Exact sciences and technology; Frequency; Parallel processing; Process design; Signal design; Signal processing algorithms; Switching systems; Systems, networks and services of telecommunications; Telecommunications; Telecommunications and information theory; Transmission and modulation (techniques and equipments); Very large scale integration; Frequency modulation; VLSI circuit; Integrated circuit; Parallel processing; Implantation; Receiver; Digital processing; Telecommunication; Algorithm
• ISSN: 0090-6778; 1558-0857
• DOI: 10.1109/TCOM.1984.1096147

The ever-increasing use of VLSI in telecommunications systems is leavening the search of new algorithms for task realizations suited to VLSI implementations of systems. Toward this search, the paper presents implementations for MF/DTMF receivers, which are based on multiplierless basic filters or primitive VLSI cells such as (1 + z^{-n}) , (1 - z^{-n}) , and (1 \pm z^{-n} + z^{-2n}) . These implementations require parallel processing and are designed to meet the requirements of a switching system.