Effective Gate Layout Methods for RF Performance Enhancement in MOSFETs

Transistor scaling with CMOS technology evolution results in f max saturation in contrast to fT improvement. This letter presents effective improvement methods for such saturated f max in the transistors fabricated by 45-nm low-standby-power CMOS technology. The primary parameter investigated is the...

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Bibliographic Details
Published in:	IEEE electron device letters Vol. 30; no. 10; pp. 1105 - 1107
Main Authors:	Kim, Han-Su, Park, Kangwook, Oh, Hansu, Jung, Eun Seung
Format:	Journal Article
Language:	English
Published:	New York, NY IEEE 01-10-2009 Institute of Electrical and Electronics Engineers The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subjects:	Applied sciences CMOS CMOS process CMOS technology Design. Technologies. Operation analysis. Testing Devices Electronics Evolution Exact sciences and technology Extrapolation Fingers Gate resistance Gates Integrated circuits layout optimization maximum oscillation frequency MOSFET circuits MOSFETs Performance gain Radio frequency radio-frequency transistors Roentgenium Saturation Semiconductor devices Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices Terrorism Transistors Performance evaluation MOSFET Oscillation frequency radio-frequency transistors Gate resistance Radiofrequency Optimization maximum oscillation frequency layout optimization Interconnection Complementary MOS technology Integrated circuit Low-power electronics
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