Effective Gate Layout Methods for RF Performance Enhancement in MOSFETs

• Published in: IEEE electron device letters Vol. 30; no. 10; pp. 1105 - 1107
• Main Authors: Kim, Han-Su, Park, Kangwook, Oh, Hansu, Jung, Eun Seung
• Format: Journal Article
• Language: English
• Published: New York, NY IEEE 01-10-2009; Institute of Electrical and Electronics Engineers; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Applied sciences; CMOS; CMOS process; CMOS technology; Design. Technologies. Operation analysis. Testing; Devices; Electronics; Evolution; Exact sciences and technology; Extrapolation; Fingers; Gate resistance; Gates; Integrated circuits; layout optimization; maximum oscillation frequency; MOSFET circuits; MOSFETs; Performance gain; Radio frequency; radio-frequency transistors; Roentgenium; Saturation; Semiconductor devices; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Terrorism; Transistors; Performance evaluation; MOSFET; Oscillation frequency; radio-frequency transistors; Gate resistance; Radiofrequency; Optimization; maximum oscillation frequency; layout optimization; Interconnection; Complementary MOS technology; Integrated circuit; Low-power electronics
• ISSN: 0741-3106; 1558-0563
• DOI: 10.1109/LED.2009.2029128

Transistor scaling with CMOS technology evolution results in f max saturation in contrast to fT improvement. This letter presents effective improvement methods for such saturated f max in the transistors fabricated by 45-nm low-standby-power CMOS technology. The primary parameter investigated is the gate layout structure through changing the gate interconnects into several folded structures. It is demonstrated that we can achieve f max of above 500 GHz and f max / fT ratio of 2.9 in the transistors through applying the proposed gate layout structures. Such high f max results from the effective reduction in the gate resistance.