Engineering change protocols for behavioral and system synthesis

• Published in: IEEE transactions on computer-aided design of integrated circuits and systems Vol. 24; no. 8; pp. 1145 - 1155
• Main Authors: Kirovski, D., Drinic, M., Potkonjak, M.
• Format: Journal Article
• Language: English
• Published: New York IEEE 01-08-2005; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Behavioral synthesis; Debugging; Design engineering; Design optimization; Design specifications; engineering change (EC); Error correction; graph coloring; Hardware; operation scheduling; Protocols; Prototypes; Rapid prototyping; register allocation; Space technology; Studies; system synthesis; Time to market; Timing
• ISSN: 0278-0070; 1937-4151
• DOI: 10.1109/TCAD.2005.850898

Rapid prototyping and development of in-circuit and FPGA-based emulators as key accelerators for fast time-to-market has resulted in a need for efficient error correction mechanisms. Fabricated or emulated prototypes upon error diagnosis require an effective engineering change (EC). We introduce a novel design methodology which consists of pre- and post-processing techniques that enable EC with minimal perturbation. Initially, in a synthesis preprocessing step, the original design specification is augmented with additional design constraints which ensure flexibility for future correction. Upon alteration of the initial design, a new post-processing technique achieves the desired functionality with near-minimal perturbation of the initially optimized design. The key contribution is a constraint manipulation technique which enables the reduction of an arbitrary EC problem into its corresponding classical synthesis problem. As a result, in both pre- and post-processing for EC, classical synthesis algorithms can be used to enable flexibility and perform the correction process. We demonstrate the developed EC methodology on a set of behavioral and system synthesis tasks.