3-D Silicon Integration and Silicon Packaging Technology Using Silicon Through-Vias

• Published in: IEEE journal of solid-state circuits Vol. 41; no. 8; pp. 1718 - 1725
• Main Authors: Knickerbocker, J.U., Patel, C.S., Andry, P.S., Tsang, C.K., Buchwalter, L.P., Sprogis, E.J., Hua Gan, Horton, R.R., Polastre, R.J., Wright, S.L., Cotte, J.M.
• Format: Journal Article Conference Proceeding
• Language: English
• Published: New York, NY IEEE 01-08-2006; Institute of Electrical and Electronics Engineers; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: 3-D; Applied sciences; Architecture; Capacitors; Carriers; Chip integration; Chips; Circuit properties; CMOS technology; Computer applications; Decoupling; Density; Design. Technologies. Operation analysis. Testing; Dielectric, amorphous and glass solid devices; Electric, optical and optoelectronic circuits; Electronics; Electronics packaging; Exact sciences and technology; high bandwidth; Integrated circuit interconnections; Integrated circuit packaging; Integrated circuit technology; Integrated circuits; integrated decoupling capacitors; Integrated optoelectronics. Optoelectronic circuits; interconnection; Microelectronic fabrication (materials and surfaces technology); Optical and optoelectronic circuits; Packages; Packaging; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Semiconductors; Silicon; silicon packaging; silicon through-vias; System-on-a-chip; Wiring; Performance evaluation; silicon packaging; Transceiver; high bandwidth; Wiring; Microelectronic fabrication; Three dimensional structure; Complementary MOS technology; Electronic packaging; integrated decoupling capacitors; Chip integration; silicon through-vias; Wafer; High performance; Die; Optoelectronics; Multichip module; Lithography; Two dimensional model; System on a chip; 3-D; Decoupling; Interconnection; Ceramic packaging; Integrated circuit; System on package; Capacitor
• ISSN: 0018-9200; 1558-173X
• DOI: 10.1109/JSSC.2006.877252

System-on-Chip (SOC) and System-on-Package (SOP) technologies each have advantages depending on application needs. As system architects and designers leverage ever-increasing CMOS technology densities, a range of two- and three-dimensional silicon integration technologies are emerging which will likely support next-generation high-volume electronic applications and may serve high-performance computing applications. This paper will discuss a few emerging technologies which offer opportunities for enhanced circuit performance, or reduced power as one example. Silicon-on-silicon integration may include three-dimensional (3-D) integration on-chip or may leverage chip stacking or chip integration on package. Common technology features include silicon through-vias, high-I/O interconnection and silicon-on-silicon either as 3-D integrated circuits, integrated chip stacks or silicon-on-silicon packages with passive function or high-bandwidth wiring. Silicon chips on silicon interposers with integrated function such as decoupling capacitors may provide a better module architecture compared to increased on-chip decoupling or off chip discrete capacitors mounted on package at the chip perimeter or underside of the package. Advanced silicon carrier package technology with fine pitch (50 mum) interconnection is described. This silicon carrier package contains silicon through-vias and offers >16times increase over standard chip I/O, a 20times to 100times increase in wiring density over traditional organic and ceramic packaging, and allows for integrated high-performance passives. Silicon carrier technology supports lithographic scaling and provides a basis for known good die (KGD) wafer testing. It may be considered for use in a number of applications including optoelectronic (OE) transceivers, silicon interposers with integrated decoupling capacitors, and mini-multi-chip modules (MMCMs) which integrate heterogeneous dies forming a single "virtual chip."