A 600-MHz single-chip multiprocessor with 4.8-GB/s internal shared pipelined bus and 512-kB internal memory

• Published in: IEEE journal of solid-state circuits Vol. 39; no. 1; pp. 184 - 193
• Main Authors: Kaneko, S., Kondo, H., Masui, N., Ishimi, K., Itou, T., Satou, M., Okumura, N., Takata, Y., Takata, H., Sakugawa, M., Higuchi, T., Ohtani, S., Sakamoto, K., Ishikawa, N., Nakajima, M., Iwata, S., Hayase, K., Nakano, S., Nakazawa, S., Yamada, K., Shimizu, T.
• Format: Journal Article
• Language: English
• Published: New York IEEE 01-01-2004; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Application software; Architecture; Buses (vehicles); CMOS; CMOS process; Computer architecture; Delay; Embedded computer systems; Embedded system; Embedded systems; Energy consumption; Multiprocessing; Multiprocessing (computers); Multiprocessor; Power consumption; Power dissipation; Protocols; Random access memory; System-on-a-chip
• ISSN: 0018-9200; 1558-173X
• DOI: 10.1109/JSSC.2003.820866

A 600-MHz single-chip multiprocessor, which includes two M32R 32-bit CPU cores , a 512-kB shared SRAM and an internal shared pipelined bus, was fabricated using a 0.15-/spl mu/m CMOS process for embedded systems. This multiprocessor is based on symmetric multiprocessing (SMP), and supports modified-exclusive-shared-invalid (MESI) cache coherency protocol. The multiprocessor inherits the advantages of previously reported single-chip multiprocessors, while its multiprocessor architecture is optimized for use as an embedded processor. The internal shared pipelined bus has a low latency and large bandwidth (4.8 GB/s). These features enhance the performance of the multiprocessor. In addition, the multiprocessor employs various low-power techniques. The multiprocessor dissipates 800 mW in a 1.5-V 600-MHz multiprocessor mode. Standby power dissipation is less than 1.5 mW at 1.5 V. Hence, the multiprocessor achieves higher performance and lower power consumption. This paper presents a single-chip multiprocessor architecture optimized for use as an embedded processor and its various low-power techniques.