Methodology and experimental verification for substrate noise reduction in CMOS mixed-signal ICs with synchronous digital circuits

• Published in: IEEE journal of solid-state circuits Vol. 37; no. 11; pp. 1383 - 1395
• Main Authors: Badaroglu, M., van Heijningen, M., Gravot, V., Compiet, J., Donnay, S., Gielen, G.G.E., De Man, H.J.
• Format: Journal Article
• Language: English
• Published: New York IEEE 01-11-2002; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Area measurement; Chips (electronics); Circuit testing; Circuits; CMOS; CMOS digital integrated circuits; CMOS process; CMOS technology; Conductivity; Decoupling; Design factors; Digital circuits; Noise reduction; Semiconductor device measurement; Synchronous; Thickness measurement
• ISSN: 0018-9200; 1558-173X
• DOI: 10.1109/JSSC.2002.803938

This paper describes substrate noise reduction techniques for synchronous CMOS circuits. Low-noise digital design techniques have been implemented and measured on a mixed-signal chip, fabricated in a 0.35 /spl mu/m CMOS process on an EPI-type substrate with 10 /spl Omega/cm EPI resistivity and 4 /spl mu/m EPI layer thickness. The test chip contains one reference design and two digital low-noise designs with the same basic architecture. Measurements show more than a factor of 2 on average in r.m.s. noise reduction with penalties of 3% in area and 4% in power for the low-noise design employing a supply-current waveform-shaping technique based on a clock tree with latencies. The second low-noise design employing separate substrate bias for both n- and p-wells, dual-supply, and on-chip decoupling achieves more than a factor of 2 reduction in r.m.s. noise, with, however, a 70% increase in area, but with a 5% decrease in power consumption.