A 5.6-ns random cycle 144-Mb DRAM with 1.4 Gb/s/pin and DDR3-SRAM interface

• Published in: IEEE journal of solid-state circuits Vol. 38; no. 11; pp. 1974 - 1980
• Main Authors: Pilo, H., Anand, D., Barth, J., Burns, S., Corson, P., Covino, J., Lamphier, S.
• Format: Journal Article
• Language: English
• Published: New York IEEE 01-11-2003; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Access time; Bandwidth; Bursting; Circuits; Compatibility; Cycle time; Decoding; Delay; Dynamic random access memory; Electrostatic discharge; Microprocessors; Packages; Plastic packaging; Random access memory; Timing; Voltage
• ISSN: 0018-9200; 1558-173X
• DOI: 10.1109/JSSC.2003.818141

This paper describes a 144-Mb DRAM that operates at a random cycle of 5.6 ns and is capable of producing data rates of 1.4 Gb/s/pin. The 121-mm/sup 2/ die is fabricated in a 0.13-/spl mu/m logic-based process with embedded DRAM. The cycle time is achieved using an early-write sensing technique that eliminates most of the timing overhead associated with the write cycle. Dynamic-precharge decoding in the subarray decode path is implemented to improve the access time. An improved data-formatting circuit is used to arrange the exit order of the eight-word burst. These circuit techniques produce latencies of 5.0 ns. The DRAM uses a DDR3-SRAM interface and is function and package compatible with industry-standard DDR3 SRAMs. Highlights of the DDR3 interface include the use of active termination circuitry on all inputs. The active termination improves the data-eye window and improves data capturing with minimum data setup and hold.