A novel robust exclusive-OR function implementation in QCA nanotechnology with energy dissipation analysis

• Published in: Journal of computational electronics Vol. 15; no. 2; pp. 455 - 465
• Main Authors: Singh, Gurmohan, Sarin, R. K., Raj, Balwinder
• Format: Journal Article
• Language: English
• Published: New York Springer US 01-06-2016; Springer Nature B.V
• Subjects: Arrays; Automata theory; Cells; Cellular automata; Circuit design; Circuits; Computation; Electrical Engineering; Energy dissipation; Engineering; Gates (circuits); Heterostructures; Logic; Mathematical and Computational Engineering; Mathematical and Computational Physics; Mechanical Engineering; Monolayers; Multilayers; Nanotechnology; Optical and Electronic Materials; Parity; Power dissipation; Power management; Quantum dots; Robustness; Semiconductors; Theoretical; Transistors; Wire; Majority gate; QCAPro; Quantum-dot cellular automata; QCADesigner; Multilayer; XOR gate
• ISSN: 1569-8025; 1572-8137
• DOI: 10.1007/s10825-016-0804-7

Numerous scientific and fundamental hindrances have resulted in a slow down of silicon technology and opened new possibilities for emerging research devices and structures. The need has arisen to expedite new methods to interface these nanostructures for computing applications. Quantum-dot Cellular Automata (QCA) is one of such computing paradigm and means of encoding binary information. QCA computing offers potential advantages of ultra-low power dissipation, improved speed and highly density structures. This paper presents a novel two-input Exclusive-OR (XOR) gate implementation in quantum-dot cellular automata nanotechnology with minimum area and power dissipation as compared to previous designs. The proposed novel QCA based XOR structure uses only 28 QCA cells with an area of
0.02
μ
m
2
and latency of 0.75 clock cycles. Also the proposed novel XOR gate is implemented in single layer without using any coplanar and multi-layer cross-over wiring facilitating highly robust and dense QCA circuit implementations. To investigate the efficacy of our proposed design in complex array of QCA structures, 4, 8, 16 and 32-bit even parity generator circuits were implemented. The proposed 4-bit even parity design occupies 9 and 50 % less area and has 12.5 and 22.22 % less latency as compared to previous designs. The 32-bit even parity design occupies 22 % less area than the best reported previous design. The proposed novel XOR structure has 28 % less switching energy dissipation, 10 % less average leakage energy dissipation and 19 % less average energy dissipation than best reported design. The simulation results verified that the proposed design offers significant improvements in terms of area, latency, energy dissipation and structural implementation requirements. All designs have been functionally verified in the QCADesigner tool for GaAs/AlGaAs heterostructure based semiconductor implementations. The energy dissipation results have been computed using an accurate QCAPro tool.