Techniques for minimizing power dissipation in scan and combinational circuits during test application

• Published in: IEEE transactions on computer-aided design of integrated circuits and systems Vol. 17; no. 12; pp. 1325 - 1333
• Main Authors: Dabholkar, V., Chakravarty, S., Pomeranz, I., Reddy, S.
• Format: Journal Article
• Language: English
• Published: New York, NY IEEE 01-12-1998; Institute of Electrical and Electronics Engineers
• Subjects: Applied sciences; Automatic test pattern generation; Automatic testing; Built-in self-test; Circuit synthesis; Circuit testing; Combinational circuits; Design. Technologies. Operation analysis. Testing; Electronics; Exact sciences and technology; Integrated circuits; Minimization; Packaging; Power dissipation; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Very large scale integration; Experimental result; VLSI circuit; Test pattern generation; Energy dissipation; Test; Complementary MOS technology; Integrated circuit; Built in self test; Computer aided design; Automatic test generation; Combinatory circuit
• ISSN: 0278-0070; 1937-4151
• DOI: 10.1109/43.736572

Reduction of power dissipation during test application is studied for scan designs and for combinational circuits tested using built-in self-test (BIST). The problems are shown to be intractable. Heuristics to solve these problems are discussed. We show that heuristics with good performance bounds can be derived for combinational circuits tested using BIST. Experimental results show that considerable reduction in power dissipation can be obtained using the proposed techniques.