A scan-based configurable, programmable, and scalable architecture for sliding window-based operations

• Published in: IEEE transactions on computers Vol. 48; no. 6; pp. 615 - 627
• Main Authors: Thibeault, C., Begin, G.
• Format: Journal Article
• Language: English
• Published: IEEE 01-06-1999
• Subjects: Architecture; Bandwidth; Circuits; Clocks; Configurable; Costs; Counting; Delay; Digital signal processing; Field programmable gate arrays; Finite impulse response filter; Hardware; Logic; Registers; Signal processing; Sliding
• ISSN: 0018-9340; 1557-9956
• DOI: 10.1109/12.773798

In this paper, a scan-based programmable, configurable, and scalable architecture is proposed. This architecture is suitable for a wide range of applications in signal processing requiring programmability and presenting high bandwidth and real-time requirements beyond the capacity of off-the-shelf DSPs or FGPAs. The architecture is specifically targeting a very common type of signal processing operation: sliding window operations (SWOs). Through various examples, the "programmability, configurability, and scalability" of the proposed architecture are illustrated. Our approach is then compared to traditional programmable architectures with coefficient registers in terms of gate count, speed (delay), and other implementation-related issues. This comparison reveals that our architecture leads to less complex solutions with comparable performance. In general, this approach can be seen as an alternative offering reduced recurrent costs at the expense of potentially higher nonrecurrent costs, which makes it very attractive for high volume production.