An In-Memory Computing SRAM Macro for Memory-Augmented Neural Network

• Published in: IEEE transactions on circuits and systems. II, Express briefs Vol. 69; no. 3; pp. 1687 - 1691
• Main Authors: Kim, Sunghoon, Lee, Wonjae, Kim, Sundo, Park, Sungjin, Jeon, Dongsuk
• Format: Journal Article
• Language: English
• Published: New York IEEE 01-03-2022; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Algorithms; Circuit design; Computation; Computer architecture; Convolutional neural networks; Data transfer (computers); Deep learning; Feature extraction; few-shot learning; in-Memory computing; l1 distance calculation; Machine learning; memory-augmented neural network; Microprocessors; mixed-signal circuits; Neural networks; Random access memory; sRAM; Static random access memory; Topology; Training; winner-take-all circuit
• ISSN: 1549-7747; 1558-3791
• DOI: 10.1109/TCSII.2021.3132063

In-Memory Computing (IMC) has been widely studied to mitigate data transfer bottlenecks in von Neumann architectures. Recently proposed IMC circuit topologies dramatically reduce data transfer requirements by performing various operations such as Multiply-Accumulate (MAC) inside the memory. In this brief, we present an SRAM macro designed for accelerating Memory-Augmented Neural Network (MANN). We first propose algorithmic optimizations for a few-shot learning algorithm employing MANN for efficient hardware implementation. Then, we present an SRAM macro that efficiently accelerates the algorithm by realizing key operations such as L1 distance calculation and Winner-Take-All (WTA) operation through mixed-signal computation circuits. Fabricated in 40nm LP CMOS technology, the design demonstrates 27.7 TOPS/W maximum energy efficiency, while achieving 93.40% and 98.28% classification accuracy for 5-way 1-shot and 5-way 5-shot learning on the Omniglot dataset, which closely matches the accuracy of the baseline algorithm.