A linearized, low-phase-noise VCO-based 25-GHz PLL with autonomic biasing

• Published in: IEEE journal of solid-state circuits Vol. 48; no. 5; pp. 1138 - 1150
• Main Authors: Sadhu, Bodhisatwa, Ferriss, Mark A., Natarajan, Arun S., Yaldiz, Soner, Plouchart, Jean-Olivier, Rylyakov, Alexander V., Valdes-Garcia, Alberto, Parker, Benjamin D., Babakhani, Aydin, Reynolds, Scott, Li, Xin, Pileggi, Larry, Harjani, Ramesh, Tierno, Jose, Friedman, Daniel
• Format: Journal Article Conference Proceeding
• Language: English
• Published: New York, NY IEEE 01-05-2013; Institute of Electrical and Electronics Engineers
• Subjects: 60 GHz; Applied sciences; Calibration; circuit noise; Circuit properties; Circuits of signal characteristics conditioning (including delay circuits); Design. Technologies. Operation analysis. Testing; digitally controlled oscillators; Electric, optical and optoelectronic circuits; electromagnetic coupling; Electronic circuits; Electronics; Exact sciences and technology; feedback; high-speed integrated circuits; integrated circuit noise; Integrated circuits; K-band; linearity; linearization; local oscillators; millimeter-wave circuits; millimeter-wave communication; millimeter-wave integrated circuits; Miscellaneous; mutual coupling; negative feedback; nonlinear circuits; oscillators; Oscillators, resonators, synthetizers; Phase locked loops; phase noise; phase-locked loop (PLL); Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; signal-to-noise ratio (SNR); Temperature measurement; Transconductance; tunable circuits and devices; Tuning; tuning range; Voltage-controlled oscillators; voltage-controlled oscillators (VCOs); Phase noise; Performance evaluation; State of the art; signal-to-noise ratio (SNR); Prototype; millimeter-wave circuits; tuning range; LC circuit; Power supply; 60 GHz; digitally controlled oscillators; voltage-controlled oscillators (VCOs); Implementation; Optimization; negative feedback; Silicon on insulator technology; feedback; Switched capacitor networks; K-band; Complementary MOS technology; nonlinear circuits; high-speed integrated circuits; millimeter-wave integrated circuits; Transconductance; Linearization; oscillators; Die; millimeter-wave communication; integrated circuit noise; Switched capacity; Low noise circuit; linearity; Voltage controlled oscillator; local oscillators; Power electronics; Calibration; phase-locked loop (PLL); Phase locked loop; tunable circuits and devices; Active component; electromagnetic coupling; Circuit noise; mutual coupling
• ISSN: 0018-9200; 1558-173X
• DOI: 10.1109/JSSC.2013.2252513

This paper describes a new approach to low-phasenoise LC VCO design based on transconductance linearization of the active devices. A prototype 25 GHz VCO based on this linearization approach is integrated in a dual-path PLL and achieves superior performance compared to the state of the art. The design is implemented in 32 nm SOI CMOS technology and achieves a phase noise of - 130 dBc/Hz at a 10 MHz offset from a 22 GHz carrier. Additionally, the paper introduces a new layout approach for switched capacitor arrays that enables a wide tuning range of 23%. More than 1500 measurements of the PLL across PVT variations were taken, further validating the proposed design. Phase noise variation across 55 dies for four different frequencies is σ < 0.6 dB. Also, phase noise variation across supply voltages of 0.7-1.5 V is 2 dB and across 60 °C temperature variation is 3 dB. At the 25 GHz center frequency, the VCO FOM T is 188 dBc/Hz. Additionally, a digitally assisted autonomic biasing technique is implemented in the PLL to provide a phase noise and power optimized VCO bias across frequency and process. Measurement results indicate the efficacy of the autonomic biasing scheme.