Titanium silicide/silicon nonohmic contact resistance for NFET's, PFET's, diffused resistors, and NPN's in a BiCMOS technology

• Published in: IEEE transactions on electron devices Vol. 42; no. 4; pp. 697 - 703
• Main Authors: Hook, T.B., Mann, R.W., Nowak, E.J.
• Format: Journal Article
• Language: English
• Published: New York, NY IEEE 01-04-1995; Institute of Electrical and Electronics Engineers
• Subjects: Applied sciences; Circuit optimization; Contact resistance; Doping; Electronics; Exact sciences and technology; FETs; Immune system; Impedance; Interfaces; Resistors; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Silicides; Silicon; Titanium; Field effect transistor; Ion implantation; Electrical properties; Complementary MOS technology; Integrated circuit; Contact resistance; Bipolar technology; Silicon; Experimental study
• ISSN: 0018-9383; 1557-9646
• DOI: 10.1109/16.372074

Self-aligned titanium silicide is often used to minimize the polysilicon and diffusion sheet resistances. Current is delivered to the channel of FET's, the body of diffused resistors, and into the active region of NPN's through the titanium silicide/silicon interface. This contact resistance can represent a significant fraction of the total device resistance for devices of small dimensions, and contributes to a loss in circuit performance. The impedance of this interface is a function of the doping level in the silicon immediately below the interface, and this doping level is a sensitive function of the heat applied to the structure after the formation of the silicide. The correspondence of FET series resistance, emitter resistance, the diffused resistor end effects and the non-ohmic nature of a contact after heat is applied is presented. Use of a rapid thermal anneal to obtain the requisite silicide characteristics while minimizing the impact on the contact resistance is demonstrated for a 0.8-/spl mu/m BiCMOS technology.< >