FLASH: Fast, Parallel, and Accurate Simulator for HLS

• Published in: IEEE transactions on computer-aided design of integrated circuits and systems Vol. 39; no. 12; pp. 4828 - 4841
• Main Authors: Choi, Young-Kyu, Chi, Yuze, Wang, Jie, Cong, Jason
• Format: Journal Article
• Language: English
• Published: New York IEEE 01-12-2020; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Acceleration; Estimation; Field programmable gate arrays; Field-programmable gate array (FPGA); Force; High level synthesis; high-level synthesis (HLS); Semantics; Simulation; simulation acceleration; Simulators; Software; source-to-source transformation
• ISSN: 0278-0070; 1937-4151
• DOI: 10.1109/TCAD.2020.2970597

A large semantic gap between a high-level synthesis (HLS) design and a low-level RTL simulation environment often creates a barrier for those who are not field-programmable gate array (FPGA) experts. Moreover, such a low-level simulation takes a long time to complete. Software HLS simulators can help bridge this gap and accelerate the simulation process; but their shortcoming is that they do not provide performance estimation. To make matters worse, we found that the current FPGA HLS commercial software simulators sometimes produce incorrect results. In order to solve these performance estimation and correctness problems while maintaining the high speed of software simulators, this article proposes a new HLS simulation flow named FLASH. The main idea behind the proposed flow is to extract scheduling information from the HLS tool and automatically construct an equivalent cycle-accurate simulation model while preserving C semantics. The experimental results show that FLASH runs three orders of magnitude faster than the RTL simulation.