Experimental evaluation and comparison of two recent Network-on-Chip routers for FPGAs

• Published in: Microprocessors and microsystems Vol. 51; pp. 134 - 141
• Main Authors: Manokaran, Jenita Priya Rajamanickam, Khalid, Mohammed A.S.
• Format: Journal Article
• Language: English
• Published: Kidlington Elsevier B.V 01-06-2017; Elsevier BV
• Subjects: Field programmable gate arrays; Field Programmable Gated Array (FPGA); Hardware description languages; Intellectual property; Interconnect; Network-on-Chip (NoC); Networks; NoC router; NoC synthesis; Routers; Studies; System on chip; Topology; Toruses; Utilization; NoC router; NoC synthesis; Network-on-Chip (NoC); Field Programmable Gated Array (FPGA)
• ISSN: 0141-9331; 1872-9436
• DOI: 10.1016/j.micpro.2017.04.008

Rapid growth in the number of Intellectual Property (IP) cores in System-on-Chip (SoC) resulted in the need for effective and scalable interconnect scheme for system components – Network-on-Chip (NoC). Router is a key component in an NoC design that impacts the overall area utilization. It is crucial to evaluate the area efficiency of NoC routers. In this paper, we evaluate and compare two recent NoC routers for Field Programmable Gated Arrays (FPGAs). The first one is generated using the automated NoC synthesis tool CONfigurable NEtwork Creation Tool (CONNECT). The second one is an NoC router manually designed using VHDL and synthesized Altera Quartus II CAD tool. Three NoC topologies namely ring, mesh and torus are used for evaluating the two routers based on area utilization metric. The routers are evaluated by varying the node sizes from 4 to 16 for each topology. For smaller NoC topologies, CONNECT router uses less area but as the NoC size increases manual router design provides up to 85% reduction in area utilization. The results presented in this paper will be useful to designers interested in NoC implementation on FPGAs.