Single-Phase Step-Up Switched-Capacitor-Based Multilevel Inverter Topology With SHEPWM

• Published in: IEEE transactions on industry applications Vol. 57; no. 3; pp. 3107 - 3119
• Main Authors: Siddique, Marif Daula, Mekhilef, Saad, Padmanaban, Sanjeevikumar, Memon, Mudasir Ahmed, Kumar, Chandan
• Format: Journal Article
• Language: English
• Published: New York IEEE 01-05-2021; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Boost topology; Capacitors; Electric converters; Energy conversion efficiency; Harmonics; Inverters; Multilevel; multilevel inverter (MLI); Multilevel inverters; Parallel operation; Pulse duration; Pulse width modulation; reduce switch count; selective harmonic elimination pulsewidth modulation (SHEPWM); switched-capacitor (SC); Switches; Topology; Voltage gain; Waveforms
• ISSN: 0093-9994; 1939-9367
• DOI: 10.1109/TIA.2020.3002182

Multilevel inverter (MLI) topologies play a crucial role in the dc-ac power conversion due to their high-quality performance and efficiency. This article aims to propose a new switched-capacitor-based boost multilevel inverter topology (SCMLI). The proposed topology consists of nine power semiconductor switches with one dc voltage source and two capacitors, capable of generating a nine-level output voltage waveform with twice voltage gain. With the addition of two switches, the proposed topology can be used for higher voltage-gain applications. Other features of the proposed topology include the self-voltage balancing of the capacitors, parallel operation of the capacitors, lower voltage stress across the switches, along with the inherent polarity changing capability. To obtain the high-quality output waveform, a selective harmonic elimination pulsewidth modulation technique is applied. In this technique, the detrimental low-order harmonics can easily be regulated and eliminated from the output voltage of MLI. The proposed topology is compared with the recently introduced SCMLI topologies considering various parameters to set the benchmark of the proposed topology. The performance of the proposed MLI is investigated through various experimental results using a laboratory prototype setup.