A Multi-ESD-Path Low-Noise Amplifier With a 4.3-A TLP Current Level in 65-nm CMOS

• Published in: IEEE transactions on microwave theory and techniques Vol. 58; no. 12; pp. 4004 - 4011
• Main Authors: Ming-Hsien Tsai, Hsu, Shawn S H, Fu-Lung Hsueh, Chewn-Pu Jou
• Format: Journal Article
• Language: English
• Published: New York IEEE 01-12-2010; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Amplifiers; Clamps; CMOS; Current measurement; Drains; Electric potential; Electrostatic discharge; electrostatic discharge (ESD); Electrostatic discharges; Logic gates; low-noise amplifier (LNA); Microwaves; Noise levels; Radio frequency; radio frequency (RF); silicon-controlled rectifier (SCR); Thyristors; Topology; transmission-line pulse (TLP); Voltage
• ISSN: 0018-9480; 1557-9670
• DOI: 10.1109/TMTT.2010.2087033

This paper studies the electrostatic discharge (ESD)-protected RF low-noise amplifiers (LNAs) in 65-nm CMOS technology. Three different ESD designs, including double-diode, modified silicon-controlled rectifier (SCR), and modified-SCR with double-diode configurations, are employed to realize ESD-protected LNAs at 5.8 GHz. By using the modified-SCR in conjunction with double-diode, a 5.8-GHz LNA with multiple ESD current paths demonstrates a 4.3-A transmission line pulse (TLP) failure level, corresponding to a ~ 6.5-kV Human-Body-Mode (HBM) ESD protection level. Under a supply voltage of 1.2 V and a drain current of 6.5 mA, the proposed ESD-protected LNA demonstrates a noise figure of 2.57 dB with an associated power gain of 16.7 dB. The input third-order intercept point (IIP3) is - 11 dBm, the input and output return losses are greater than 15.9 and 20 dB, respectively.