State Variable Extraction and Partitioning to Reduce Problem Complexity for ATPG and Design Validation

• Published in: IEEE transactions on computer-aided design of integrated circuits and systems Vol. 25; no. 10; pp. 2275 - 2282
• Main Authors: Qingwei Wu, Hsiao, M.S.
• Format: Journal Article
• Language: English
• Published: New York IEEE 01-10-2006; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Algorithms; Automatic test pattern generation; Automatic test pattern generation (ATPG); Circuit faults; Circuit simulation; Circuit testing; Circuits; Data mining; Design engineering; design validation; Explosions; Flip-flops; logic simulation; Logic testing; Mathematical analysis; Mathematical models; Partitioning; Sequential analysis; Sequential circuits; Studies; Vectors (mathematics)
• ISSN: 0278-0070; 1937-4151
• DOI: 10.1109/TCAD.2005.859512

This paper presents a new algorithm to extract characteristic flip-flops, which form a characteristic state set, using state-correlation information. The extracted characteristic state set allows us to focus on a significantly smaller set of flip-flops while ignoring other flip-flops, thereby simplifying the target problem and reducing state explosion in very large sequential circuits. Next, partitioning is applied only on the characteristic state variables, and partial state transition graphs (STGs) are built. During test generation, no specific fault or design error is targeted; instead, test vectors are generated using a twofold criteria: 1) whether the vector will expand the overall STGs and 2) whether this vector will break the relationship among flip-flops within the correlated sets. While generating vectors, state and transition exploration histories for each state group are maintained by dynamically constructing partial STGs for all state groups. By limiting a maximum size any state group can be, maintaining the complete state and transition exploration histories for each state group is feasible even for very large sequential circuits. Experiments showed that our extraction algorithm can reduce the original complete state set by up to 97%. In addition, with the reduced state variables, it achieves not only equal or better coverages for both stuck-at faults and design errors, the execution time is also significantly reduced due to the much fewer flip-flops that this paper needs to consider. For some large sequential circuits, highest coverages have been obtained