A 22-ns 1-Mbit CMOS high-speed DRAM with address multiplexing

• Published in: IEEE journal of solid-state circuits Vol. 24; no. 5; pp. 1198 - 1205
• Main Authors: Lu, N.C.-C., Bronner, G.B., Kitamura, K., Scheuerlein, R.E., Henkels, W.H., Dhong, S.H., Katayama, Y., Kirihata, T., Niijima, H., Franch, R.L., Wang, W., Nishiwaki, M., Pesavento, F.L., Rajeevakumar, T.V., Sakaue, Y., Suzuki, Y., Iguchi, Y., Yano, E.
• Format: Journal Article
• Language: English
• Published: New York, NY IEEE 01-10-1989; Institute of Electrical and Electronics Engineers
• Subjects: Aluminum; Applied sciences; Boron; Circuits; CMOS technology; Electronics; Exact sciences and technology; Integrated circuits; Integrated circuits by function (including memories and processors); Laboratories; MOS devices; Random access memory; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Testing; Voltage; Wiring; Random access memory(RAM); Circuit design; Complementary MOS technology; Memory; Integrated circuit; Dynamical storage; Manufacturing
• ISSN: 0018-9200; 1558-173X
• DOI: 10.1109/JSSC.1989.572579

Describes a 1-Mbit high-speed DRAM (HSDRAM), which has a nominal random access time of less than 27 ns and a column access time of 12 ns with address multiplexing. A double-polysilicon double-metal CMOS technology having PMOS arrays inside n-wells was developed with an average 1.3- mu m feature size. The chip has also been fabricated in a 0.9*shrunken version with an area of 67 mm/sup 2/, showing a 22-ns access time. The chip power consumption is lower than 500 mW at 60-ns cycle time. This HSDRAM, which provides SRAM-like speed while retaining DRAM-like density, allows DRAMs to be used in a broad new range of applications.< >