Investigation of Trap Spacing for the Amorphous State of Phase-Change Memory Devices

• Published in: IEEE transactions on electron devices Vol. 58; no. 12; pp. 4370 - 4376
• Main Authors: Jeyasingh, R. G. D., Kuzum, D., Wong, H-S P.
• Format: Journal Article
• Language: English
• Published: New York, NY IEEE 01-12-2011; Institute of Electrical and Electronics Engineers; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Applied sciences; Design. Technologies. Operation analysis. Testing; Electrical resistance measurement; Electron traps; Electronics; Exact sciences and technology; hbox{1}/f noise; Heating; Integrated circuits; Integrated circuits by function (including memories and processors); Noise; Phase change; Phase change materials; Resistance; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; subthreshold conduction; Threshold voltage; trap states; Localized state; Amorphous material; Voltage current curve; Random access memory; Phase change; trap states; Spacing; 1/f noise; Amorphous state; Switching; Electric field; Non volatile memory; Integrated circuit; PCM material; Voltage drift; subthreshold conduction
• ISSN: 0018-9383; 1557-9646
• DOI: 10.1109/TED.2011.2169798

The subthreshold conduction in the amorphous state of the phase-change material is dominated by the hopping of the carriers through the trap states or localized states with the assistance of the electric field across the material. It is important to understand the nature and number of these traps to properly model the physics of the conduction, threshold switching, and drift in phase-change materials. In this paper, we present a device structure and a methodology to extract the trap spacing directly from the I-V characteristics of the device. Furthermore, the dependence of the trap spacing on the amorphous region thickness, reset voltage, and drift is also discussed. These results are then correlated with the 1/f noise measurements of the device.