Design and implementation of efficient QCA full-adders using fault-tolerant majority gates

• Published in: The Journal of supercomputing Vol. 78; no. 6; pp. 8056 - 8080
• Main Authors: Bravo-Montes, J. A., Martín-Toledano, A., Sánchez-Macián, A., Ruano, O., Garcia-Herrero, F.
• Format: Journal Article
• Language: English
• Published: New York Springer US 2022; Springer Nature B.V
• Subjects: Cellular automata; Compilers; Computer Science; Energy dissipation; Fault tolerance; Interpreters; Low temperature environments; Manufacturing; Power consumption; Processor Architectures; Programming Languages; Design; QCADesigner; Fault-tolerant; Quantum cellular automata
• ISSN: 0920-8542; 1573-0484
• DOI: 10.1007/s11227-021-04247-9

CMOS technology is facing physical limitations in scaling the manufacturing process. Therefore, to deepen the development of better designs in a smaller area, it is necessary to look for other alternatives. One of the most studied approaches is Quantum Cellular Automata (QCA). However, it has the disadvantage of its reliability during the manufacturing processes, with high error rates that are difficult to improve. To contribute to the design of more reliable operators based on this technology, new fault-tolerant full-adders are presented in this paper. The proposed solutions improve area up to 57.14%, total energy dissipation up to 36.27%, and average energy dissipation per cycle up to 36.22% compared to those previously proposed. This reduction in power consumption is especially important to make QCA more competitive as it has to operate in low-temperature environments.