Capacitance matching by optimizing the geometry of a ferroelectric HfO2-based gate for voltage amplification

• Published in: Journal of computational electronics Vol. 20; no. 3; pp. 1209 - 1215
• Main Authors: Chen, K.-T., Hsiang, K.-Y., Liao, C.-Y., Chang, S.-H., Hsieh, F.-C., Liu, J.-H., Chiang, S.-H., Liang, H., Chang, S. T., Lee, M. H.
• Format: Journal Article
• Language: English
• Published: New York Springer US 01-06-2021; Springer Nature B.V
• Subjects: Amplification; Capacitance; CMOS; Electric fields; Electric potential; Electrical Engineering; Engineering; Ferroelectric materials; Ferroelectricity; Field effect transistors; Geometry; Matching; Mathematical and Computational Engineering; Mathematical and Computational Physics; Mechanical Engineering; Metal oxide semiconductors; Optical and Electronic Materials; Optimization; Semiconductor devices; Simulation; Theoretical; Voltage; Negative capacitance (NC); Capacitance matching; Optoelectronic; Steep switch; FinFET
• ISSN: 1569-8025; 1572-8137
• DOI: 10.1007/s10825-021-01701-y

The voltage amplification of a ferroelectric layer was studied for advanced complementary metal–oxide–semiconductor (CMOS) applications. To match the capacitance for negative-capacitance field-effect transistors (NC-FETs), a method of adjusting the MOS capacitance is proposed by optimizing the width (
W
) and height/depth (
H
) in two types of ferroelectric gate-stack 2D metal-oxide semiconductor capacitor (MOSCAP) structures: a fin-like structure and a trench structure. The capacitance of the semiconductor was modeled to match that of the ferroelectric films to obtain hysteresis-free operation (Δ
V
T
 = 
V
T
, for –
V
T,rev
 ~ 0) and achieve voltage amplification (
A
V
). The optimized conditions are found to be
H
 = 19.3 nm and 24.3 nm to achieve the criterion with
A
V
 > 50 for the fin-like and trench structure, respectively. Subsequently, the structure was extended to a three-dimensional (3D) fin-shaped field-effect transistor (FinFET) to evaluate the effects of varying geometrical parameters such as the fin spacing (
F
S
). Tuning
F
S
can not only enhance the on-current but also decrease the subthreshold swing in the off-current region. For the FET, the use of the optimum
F
S
value of 30 nm helps the FinFETs achieve capacitance matching with
A
V
 > 30. The subthreshold swing of the NC-FinFET is improved by about 47% for
H
FinFET
/
W
FinFET
 ~ 3 and
F
s
/
H
FinFET
 ~ 1.2 as compared with the conventional FinFET. The concept of coupling the polarized Hf-based oxide in NC-FETs that is demonstrated to be feasible herein is thus practicable using current CMOS architectures.