Pin density technique for congestion estimation and reduction of optimized design during placement and routing

• Published in: Applied nanoscience Vol. 13; no. 3; pp. 1819 - 1828
• Main Authors: Karimullah, Shaik, Vishnuvardhan, D.
• Format: Journal Article
• Language: English
• Published: Cham Springer International Publishing 01-03-2023; Springer Nature B.V
• Subjects: Algorithms; Chemistry and Materials Science; Circuit design; Congestion; Density; Design engineering; Design optimization; Design parameters; Estimation; Floorplans; Graph theory; Heuristic methods; Integrated circuits; Materials Science; Membrane Biology; Nanochemistry; Nanotechnology; Nanotechnology and Microengineering; Optimization algorithms; Original Article; Placement; Reduction; Congestion; VLSI; Pin density; Placement; HIS algorithm
• ISSN: 2190-5509; 2190-5517
• DOI: 10.1007/s13204-021-02173-z

This work presents an estimation of design parameters for placement and routing in IC fabrication with the help of the existing Floorplan, done using the Optimization algorithm in Circuit Design Engineering. It will be extremely helpful in testing the outcome possibility of IC Design. Because of underestimation of Placement and Routing Congestion issues IC implementation can face exceptionally nonlinear issues during its operation. Regular Optimization calculations are not the best approaches for profoundly estimating nonlinear characteristics in IC Design. So advanced tools like ICC2, VIVADO, CADENCE, VIRTUOSO, etc. are made available to search for calculations and get the actual parameters to reach optimal Placement and Routing for efficient Physical Design. This paper presents an estimation of routing congestion in both horizontal and vertical directions for a silicon chip area and reducing the density of excessive routing using the Pin Density Technique (PDT). Meta-heuristic calculations have gotten progressively famous over the recent twenty years. The most limited way is an old-style issue in graph theory, it is additionally one of the traditional issues in the field of Optimization but failed to give accurate information about Placement and Routing. To overcome this issue we make use of the Optimized model generated by the Improved Harmonic Search Optimization algorithm, and incorporating the optimized floorplan details into the ICC II tool for the estimation and reduction of congestion during routing in VLSI Circuit Design. The simulation tool used in this work is more advanced and effective in evaluation and estimation of required parameters.