A review of in-memory computing for machine learning: architectures, options

• Published in: International journal of Web information systems Vol. 20; no. 1; pp. 24 - 47
• Main Authors: Snasel, Vaclav, Dang, Tran Khanh, Kueng, Josef, Kong, Lingping
• Format: Journal Article
• Language: English
• Published: Bingley Emerald Publishing Limited 05-02-2024; Emerald Group Publishing Limited
• Subjects: Algorithms; Application specific integrated circuits; Artificial intelligence; Big Data; Central processing units; Computation; Computer architecture; Cost reduction; CPUs; Data analysis; Data processing; Design optimization; Energy consumption; Evolution; Field programmable gate arrays; Graphics processing units; Hardware; Heterogeneity; Machine learning; Neural networks; Performance enhancement; Performance measurement; Random access memory; In-memory computing; In-memory accelerator; Deep neural network; Machining learning
• ISSN: 1744-0084; 1744-0092; 1744-0084
• DOI: 10.1108/IJWIS-08-2023-0131

Purpose
This paper aims to review in-memory computing (IMC) for machine learning (ML) applications from history, architectures and options aspects. In this review, the authors investigate different architectural aspects and collect and provide our comparative evaluations.
Design/methodology/approach
Collecting over 40 IMC papers related to hardware design and optimization techniques of recent years, then classify them into three optimization option categories: optimization through graphic processing unit (GPU), optimization through reduced precision and optimization through hardware accelerator. Then, the authors brief those techniques in aspects such as what kind of data set it applied, how it is designed and what is the contribution of this design.
Findings
ML algorithms are potent tools accommodated on IMC architecture. Although general-purpose hardware (central processing units and GPUs) can supply explicit solutions, their energy efficiencies have limitations because of their excessive flexibility support. On the other hand, hardware accelerators (field programmable gate arrays and application-specific integrated circuits) win on the energy efficiency aspect, but individual accelerator often adapts exclusively to ax single ML approach (family). From a long hardware evolution perspective, hardware/software collaboration heterogeneity design from hybrid platforms is an option for the researcher.
Originality/value
IMC’s optimization enables high-speed processing, increases performance and analyzes massive volumes of data in real-time. This work reviews IMC and its evolution. Then, the authors categorize three optimization paths for the IMC architecture to improve performance metrics.