Low power PLL with reduced reference spur realized with glitch-free linear PFD and current splitting CP

• Published in: Analog integrated circuits and signal processing Vol. 93; no. 1; pp. 29 - 39
• Main Authors: Abdul Majeed, K. K., Kailath, Binsu J.
• Format: Journal Article
• Language: English
• Published: New York Springer US 01-10-2017; Springer Nature B.V
• Subjects: Charge pumps; Circuits and Systems; Electrical Engineering; Engineering; Leakage current; Linearity; Low noise; Military communications; Mobile communication systems; Noise reduction; Receivers; Signal,Image and Speech Processing; Splitting; Wireless communications; Reference spur; Leakage current; Charge pump; Phase frequency detector; Voltage controlled oscillator; Phase locked loop
• ISSN: 0925-1030; 1573-1979
• DOI: 10.1007/s10470-017-1013-4

This work has been focused on designing a phase locked loop (PLL) operating in the GHz range with reduced reference spur and power requirement suitable for wireless communication applications such as wireless receivers, serial link trans-receivers and military communication. A novel PLL is designed using a linear PFD which is free of glitches, dead zone and blind zone, a charge pump based on current splitting technique and a modified current starved differential delay cell (MCSDD) VCO. Performance characteristics of proposed PLL obtained from circuit simulation in Cadence have been compared with simulation results from MATLAB. φ–V characteristics of linear PFD has been found to offer better linearity from −π to π as blind zone and dead zone are eliminated. Glitches at output of PFD have also been eliminated. Charge pump based on current splitting technique in combination with proposed PFD has been found to be effective in reducing leakage current to 3 nA. Tuning range of 98.12% with maximum operating frequency of 4.27 GHz has been obtained for the MCSDD VCO. PLL built with above circuits has been found to offer reference spur of −75.92 dBc@20 MHz offset, phase noise of −113.5 dBc/Hz@100 kHz and lock time of 2.95 μs. It is believed to be the first report of linear PFD in which glitches are completely eliminated. The PLL would be suitable for low power, low noise and high frequency applications as required in mobile communications operating around 20 MHz, to be derived from the VCO when set to generate a frequency of 2.56 GHz.