Synthesis of application specific instruction sets

• Published in: IEEE transactions on computer-aided design of integrated circuits and systems Vol. 14; no. 6; pp. 663 - 675
• Main Authors: Ing-Jer Huang, Despain, A.M.
• Format: Journal Article
• Language: English
• Published: New York, NY IEEE 01-06-1995; Institute of Electrical and Electronics Engineers
• Subjects: Application software; Applied sciences; Assembly; Computer aided instruction; Computer interfaces; Design. Technologies. Operation analysis. Testing; Electronics; Exact sciences and technology; Hardware; Instruction sets; Integrated circuits; Microprocessors; Processor scheduling; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Simulated annealing; System performance; Theoretical study; Microprocessor; Custom circuit; Computer aided design; Integrated circuit
• ISSN: 0278-0070; 1937-4151
• DOI: 10.1109/43.387728

In instruction set serves as the interface between hardware and software in a computer system. In an application specific environment, the system performance can be improved by designing an instruction set that matches the characteristics of hardware and the application. We present a systematic approach to generate application-specific instruction sets so that software applications can be efficiently mapped to a given pipelined micro-architecture. The approach synthesizes instruction sets from application benchmarks, given a machine model, an objective function, and a set of design constraints. In addition, assembly code is generated to show how the benchmarks can be compiled with the synthesized instruction set. The problem of designing instruction sets is formulated as a modified scheduling problem. A binary tuple is proposed to model the semantics of instructions and integrate the instruction formation process into the scheduling process. A simulated annealing scheme is used to solve for the schedules. Experiments have shown that the approach is capable of synthesizing powerful instructions for modern pipelined microprocessors, and running with reasonable time and a modest amount of memory for large applications.< >