Latency- and hazard-free volume memory architecture for direct volume rendering

• Published in: Computers & graphics Vol. 21; no. 2; pp. 179 - 187
• Main Authors: De Boer, M., Gröpl, A., Hesser, J., Männer, R.
• Format: Journal Article
• Language: English
• Published: Elsevier Ltd 01-03-1997
• ISSN: 0097-8493; 1873-7684
• DOI: 10.1016/S0097-8493(96)00081-7

Real-time direct volume rendering (ray-casting or volume ray-tracing) is achieved by problem specific rendering architectures. The performance of these architectures is however limited by the access to the volume memory. Although many different volume memory architectures have been proposed and realized, none of them uses the read-out-gain provided by new DRAM interfaces like Rambus-DRAM, SDRAM
etc. In this paper a solution is presented that allows profit from these new interfaces. The key feature of the new architecture is a multi-level cache system with software prefetching and latency hiding. By allowing the rendering pipeline processor to operate at up to 200 MHz, a 512
3 data set stored in a single memory module can be rendered at 3.125 Hz. An even higher performance is possible from the DRAM side but is limited by current SRAM and processor speeds.