The total delay fault model and statistical delay fault coverage

• Published in: IEEE transactions on computers Vol. 41; no. 6; pp. 688 - 698
• Main Authors: Park, E.S., Mercer, M.R., Williams, T.W.
• Format: Journal Article
• Language: English
• Published: New York, NY IEEE 01-06-1992; Institute of Electrical and Electronics Engineers
• Subjects: Applied sciences; Circuit faults; Circuit testing; Clocks; Delay effects; Delay systems; Design. Technologies. Operation analysis. Testing; Electronics; Exact sciences and technology; Fault detection; Integrated circuits; Logic testing; Propagation delay; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; System testing; Timing; Logic circuit; Delay circuit; Propagation; Test; Integrated circuit; Metric; Computer system; Timing; Failures
• ISSN: 0018-9340; 1557-9956
• DOI: 10.1109/12.144621

Delay testing at the operational system clock rate can detect system timing failures caused by delay faults. However, delay fault coverage in terms of the percentage of the number of tested faults may not be an effective measure of delay testing. A quantitative delay fault coverage model to provide a figure of merit for delay testing is presented. System sensitivity of a path to a delay fault along that path and the effectiveness of a delay test are described in terms of the propagation delay of the path under test and the delay defect size. A new statistical delay fault coverage model is established. A defect level model is also proposed as a function of the yield of a manufacturing process and the new statistical delay fault coverage. A new delay testing strategy driven by the defect level for delay faults is proposed.< >