Dual-DFE read/write channel IC for hard-disk drives

The channel IC described here achieves data rates of 380 Mb/s at performance levels that improve in various directions upon the state of the art. It accomplishes these feats in a mature 1 /spl mu/m CBiCMOS technology at a readmode power consumption of only 800 mW. The paper discusses some of the und...

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Bibliographic Details
Published in:	IEEE transactions on magnetics Vol. 34; no. 1; pp. 172 - 177
Main Authors:	Bergmans, J.W.M., Voorman, J.O., Groenewold, G., Hollmann, H.D.L., De Jong, G.W., Lugthart, M.L., Pothast, J., Ramaekers, J.A.M., Ramalho, J.N.V., Van Riel, L.F.H., Veenstra, H., Wong-Lam, H.W., Medley, D.H., Bhandari, S., Dakshinamurthy, R., Davis, P.F., Mosqueda, G.S., Raman, S., Wang, J.
Format:	Journal Article
Language:	English
Published:	IEEE 01-01-1998
Subjects:	Bandwidth Circuit noise Clocks Ear Energy consumption Frequency synthesizers Hard disks Modulation coding Random sequences Semiconductor device noise
Online Access:	Get full text
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Summary:	The channel IC described here achieves data rates of 380 Mb/s at performance levels that improve in various directions upon the state of the art. It accomplishes these feats in a mature 1 /spl mu/m CBiCMOS technology at a readmode power consumption of only 800 mW. The paper discusses some of the underlying architectural concepts.
Bibliography:	ObjectType-Article-2 SourceType-Scholarly Journals-1 ObjectType-Feature-1 content type line 23
ISSN:	0018-9464 1941-0069
DOI:	10.1109/20.663513